The present invention is related to clocked regenerative latch circuits, and, more particularly, to a high-speed latch circuits useful as input buffers in a BiCMOS integrated circuit.
BiCMOS integrated circuits are semiconductor devices in which bipolar technology is combined with complementary metal oxide semiconductor (CMOS) technology. In such an BiCMOS integrated circuit, the higher speed, greater power-consuming bipolar transistor circuits are located at the suitable locations in the semiconductor device to use the speed and drive capabilities inherent in bipolar transistors. The CMOS circuits are used wherever higher packing densities and lower power consumption of CMOS circuits are suitable.
Some BiCMOS integrated circuit communicate with the outside world with signal levels appropriate for bipolar logic circuits. CMOS level signals are used within the device. A common bipolar logic used in BiCMOS devices is emitter-coupled logic (ECL) which has a signal range from -0.9 to -1.7 volts. On the other hand, CMOS signals swing in a 5-volt range.
A goal, then, is to bring ECL signals into the BiCMOS integrated circuit and translated into CMOS levels as quickly as possible. A more general goal is to buffer and to translate ECL signals for use by the CMOS logic circuits. The present invention is a substantial advance toward that goal.